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DS21Q58 E1 Quad Transceiver
18 of 74
8.1 Power-Up Sequence
On power-up and after the supplies are stable, the DS21Q58 should be configured for operation by writing to all the
internal registers (this includes setting the test register to 00h) since the contents of the internal registers cannot be
predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry. (It
takes the device about 40ms to recover from the LIRST bit being toggled.) After the SYSCLK input is stable, the
ESR bits (CCR4.5 and CCR4.6) should be toggled from 0 to 1 (this step can be skipped if the elastic store is
disabled).
Register Name:
RCR
Register Description:
Receive Control Register
Register Address:
10 Hex
Bit #
7
6
5
4
3
2
1
0
Name
RSMF
RSM
RSIO
RESE
—
FRC
SYNCE
RESYNC
NAME
BIT
FUNCTION
RSMF
7
RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the
multiframe mode (RCR.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries.
1 = RSYNC outputs CRC4 multiframe boundaries.
RSM
6
RSYNC Mode Select
0 = frame mode (see the timing diagrams in Section 24.1)
1 = multiframe mode (see the timing diagrams in Section 24.1)
RSIO
5
RSYNC I/O Select. (Note: This bit must be set to 0 when RCR .4 = 0.)
0 = RSYNC is an output (depends on RCR.6)
1 = RSYNC is an input (only valid if elastic store enabled)
RESE
4
Receive Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
—
3
Unused. Should be set = 0 for proper operation.
FRC
2
Frame Resync Criteria
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
SYNCE
1
Sync Enable
0 = auto resync enabled
1 = auto resync disabled
RESYNC
0
Resync. When toggled from low to high, a resync is initiated. Must be cleared and
set again for a subsequent resync.
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